CPM Electrical Characteristics
Table 28. I2C Timing (SCL < 100 KHZ) (continued)
Characteristic
All Frequencies
Num
Unit
Min
Max
210 SDL/SCL fall time
—
300
—
ns
211
Stop condition setup time
4.7
µs
1 SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) × pre_scaler × 2).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
2
Table 29 provides the I C (SCL > 100 KHz) timings.
Table 29. I2C Timing (SCL > 100 KHZ)
All Frequencies
Num
Characteristic
Expression
Unit
Min
Max
200 SCL clock frequency (slave)
200 SCL clock frequency (master) 1
202 Bus free time between transmissions
203 Low period of SCL
fSCL
fSCL
—
0
BRGCLK/48
Hz
Hz
s
BRGCLK/16512
1/(2.2 × fSCL)
1/(2.2 × fSCL)
1/(2.2 × fSCL)
1/(2.2 × fSCL)
1/(2.2 × fSCL)
0
BRGCLK/48
—
—
—
s
204 High period of SCL
—
—
s
205 Start condition setup time
206 Start condition hold time
207 Data hold time
—
—
s
—
—
s
—
—
—
s
208 Data setup time
—
1/(40 × fSCL)
—
s
209 SDL/SCL rise time
—
1/(10 × fSCL)
1/(33 × fSCL)
—
s
210 SDL/SCL fall time
—
—
s
211
Stop condition setup time
—
1/2(2.2 × fSCL)
s
1 SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) × pre_scaler × 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
MPC885/MPC880 Hardware Specifications, Rev. 3
68
Freescale Semiconductor
FREESCALE [ Freescale ]
