Enhanced Three-Speed Ethernet (eTSEC)
Figure 15 shows the TBI receive AC timing diagram.
t
t
TRXR
TRX
TSECn_RX_CLK1
t
t
TRXH
TRXF
RCG[9:0]
Valid Data
Valid Data
t
TRDVKH
t
t
SKTRX
TRDXKH
TSECn_RX_CLK0
t
t
TRDXKH
TRXH
t
TRDVKH
Figure 15. TBI Receive AC Timing Diagram
8.2.5
TBI Single-Clock Mode AC Specifications
When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant
eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1, a 125-MHz TBI receive clock
is supplied on the TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode,
whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied
on the TSEC_GTX_CLK125 pin in all TBI modes.
A summary of the single-clock TBI mode AC specifications for receive appears in Table 32.
Table 32. TBI single-clock Mode Receive AC Timing Specification
Parameter/Condition
RX_CLK clock period
Symbol
Min
Typ
Max
Unit
t
7.5
40
—
8.0
50
—
—
—
—
—
8.5
60
ns
%
TRRX
t
TRRH/TRRX
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
t
250
1.0
1.0
—
ps
ns
ns
ns
ns
TRRJ
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RCG[9:0] setup time to RX_CLK rising edge
RCG[9:0] hold time to RX_CLK rising edge
t
—
TRRR
t
—
TRRF
t
t
2.0
1.0
TRRDVKH
TRRDXKH
—
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
35
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