Enhanced Three-Speed Ethernet (eTSEC)
Figure 11 shows the MII transmit AC timing diagram.
t
t
MTXR
MTX
TX_CLK
t
t
MTXF
MTXH
TXD[3:0]
TX_EN
TX_ER
t
MTKHDX
Figure 11. MII Transmit AC Timing Diagram
8.2.3.2
MII Receive AC Timing Specifications
Table 29 provides the MII receive AC timing specifications.
Table 29. MII Receive AC Timing Specifications
1
Parameter/Condition
RX_CLK clock period 10 Mbps
Symbol
Min
Typ
Max
Unit
2
t
—
—
400
40
—
—
—
ns
ns
%
MRX
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
t
MRX
t
/t
35
65
—
MRXH MRX
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise (20%–80%)
RX_CLK clock fall time (80%–20%)
Notes:
t
10.0
10.0
1.0
1.0
—
ns
ns
ns
ns
MRDVKH
t
—
—
MRDXKH
2
t
—
4.0
4.0
MRXR
2
t
—
MRXF
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes MII receive
(first two letters of functional block)(reference)(state)(signal)(state)
MRDVKH
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock reference (K)
MRX
going to the high (H) state or setup time. Also, t
symbolizes MII receive timing (GR) with respect to the time data input
MRDXKL
signals (D) went invalid (X) relative to the t
clock reference (K) going to the low (L) state or hold time. Note that, in general,
MRX
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
MRX
with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
Figure 12 provides the AC test load for eTSEC.
Output
Z = 50 Ω
0
LV /2
DD
R = 50 Ω
L
Figure 12. eTSEC AC Test Load
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
32
FREESCALE [ Freescale ]
