Enhanced Three-Speed Ethernet (eTSEC)
Figure 8 shows the GMII transmit AC timing diagram.
t
t
GTXR
GTX
GTX_CLK
t
t
GTXF
GTXH
TXD[7:0]
TX_EN
TX_ER
t
GTKHDX
t
GTKHDV
Figure 8. GMII Transmit AC Timing Diagram
8.2.2.2
GMII Receive AC Timing Specifications
Table 27 provides the GMII receive AC timing specifications.
Table 27. GMII Receive AC Timing Specifications
1
Parameter/Condition
RX_CLK clock period
Symbol
Min
Typ
Max
Unit
t
—
35
2.0
0
8.0
—
—
—
—
—
—
75
—
ns
ns
ns
ns
ns
ns
GRX
RX_CLK duty cycle
t
/t
GRXH GRX
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise (20%-80%)
RX_CLK clock fall time (80%-20%)
Notes:
t
GRDVKH
t
—
GRDXKH
2
t
—
—
1.0
1.0
GRXR
2
t
GRXF
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes GMII receive
(first two letters of functional block)(reference)(state)(signal)(state)
GRDVKH
timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t clock reference (K)
RX
going to the high state (H) or setup time. Also, t
input signals (D) went invalid (X) relative to the t
symbolizes GMII receive timing (GR) with respect to the time data
clock reference (K) going to the low (L) state or hold time. Note that, in
GRDXKL
GRX
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention
GRX
is used with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
Figure 9 provides the AC test load for eTSEC.
Output
LV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 9. eTSEC AC Test Load
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
30
FREESCALE [ Freescale ]
