Enhanced Three-Speed Ethernet (eTSEC)
A summary of the FIFO AC specifications appears in
and
Table 24. FIFO Mode Transmit AC Timing Specification
Parameter/Condition
TX_CLK, GTX_CLK clock period
TX_CLK, GTX_CLK duty cycle
TX_CLK, GTX_CLK peak-to-peak jitter
Rise time TX_CLK (20%–80%)
Fall time TX_CLK (80%–20%)
FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
Symbol
t
FIT
t
FITH
/t
FIT
t
FITJ
t
FITR
t
FITF
t
FITDV
t
FITDX
Min
5.3
45
—
—
—
2.0
0.5
Typ
8.0
50
—
—
—
—
—
Max
100
55
250
0.75
0.75
—
3.0
Unit
ns
%
ps
ns
ns
ns
ns
Table 25. FIFO Mode Receive AC Timing Specification
Parameter/Condition
RX_CLK clock period
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
Symbol
t
FIR
t
FIRH
/t
FIR
t
FIRJ
t
FIRR
t
FIRF
t
FIRDV
t
FIRDX
Min
5.3
45
—
—
—
1.5
0.5
Typ
8.0
50
—
—
—
—
—
Max
100
55
250
0.75
0.75
—
—
Unit
ns
%
ps
ns
ns
ns
ns
Note:
1. The minimum cycle period of the TX_CLK and RX_CLK is dependent on the maximum platform frequency of t he speed bins
the part belongs to as well as the FIFO mode under operation. Refer to
Timing diagrams for FIFO appear in
and
t
FIT
GTX_CLK
t
FITH
t
FITDV
TXD[7:0]
TX_EN
TX_ER
t
FITDX
t
FITF
t
FITR
Figure 6. FIFO Transmit AC Timing Diagram
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
28
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
