Enhanced Three-Speed Ethernet (eTSEC)
A summary of the FIFO AC specifications appears in Table 24 and Table 25.
Table 24. FIFO Mode Transmit AC Timing Specification
Parameter/Condition
TX_CLK, GTX_CLK clock period
Symbol
Min
Typ
Max
Unit
t
5.3
45
—
8.0
50
—
—
—
—
—
100
55
ns
%
FIT
TX_CLK, GTX_CLK duty cycle
t
/t
FITH FIT
TX_CLK, GTX_CLK peak-to-peak jitter
Rise time TX_CLK (20%–80%)
t
250
0.75
0.75
—
ps
ns
ns
ns
ns
FITJ
t
—
FITR
Fall time TX_CLK (80%–20%)
t
—
FITF
FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
t
2.0
0.5
FITDV
FITDX
t
3.0
Table 25. FIFO Mode Receive AC Timing Specification
Parameter/Condition
Symbol
Min
Typ
Max
Unit
RX_CLK clock period
RX_CLK duty cycle
t
5.3
45
—
8.0
50
—
—
—
—
—
100
55
ns
%
FIR
t
/t
FIRH FIR
RX_CLK peak-to-peak jitter
t
250
0.75
0.75
—
ps
ns
ns
ns
ns
FIRJ
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
Note:
t
—
FIRR
t
—
FIRF
t
1.5
0.5
FIRDV
FIRDX
t
—
1. The minimum cycle period of the TX_CLK and RX_CLK is dependent on the maximum platform frequency of t he speed bins
the part belongs to as well as the FIFO mode under operation. Refer to Section 4.5, “Platform to FIFO Restrictions.”
Timing diagrams for FIFO appear in Figure 6 and Figure 7.
t
t
t
FITR
FIT
FITF
GTX_CLK
t
FITH
t
t
FITDX
FITDV
TXD[7:0]
TX_EN
TX_ER
Figure 6. FIFO Transmit AC Timing Diagram
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
28
FREESCALE [ Freescale ]
