Enhanced Three-Speed Ethernet (eTSEC)
Table 23. GMII, MII, RMII, TBI, RGMII, RTBI, and FIFO DC Electrical Characteristics
Parameters
Symbol
LV /TV
Min
Max
Unit
Notes
Supply voltage 2.5 V
Output high voltage (LV /TV = Min,
2.37
2.00
2.63
V
V
1, 2
—
DD
DD
V
LV /TV + 0.3
DD DD
DD
DD
OH
I
= –1.0 mA)
OH
Output low voltage (LV /TV = Min,
V
OL
GND –0.3
0.40
V
—
DD
DD
I
= 1.0 mA)
OL
Input high voltage
Input low voltage
V
1.70
–0.3
—
LV /TV + 0.3
V
V
—
—
IH
DD
DD
V
I
0.90
IL
Input high current (V = LV , V = TV
)
10
—
μA
μA
1, 2, 3
3
IN
DD IN
DD
IH
Input low current (V = GND)
I
–15
IN
IL
Notes:
1. LV supports eTSECs 1 and 2.
DD
2. TV supports eTSECs 3 and 4.
DD
3. Note that the symbol V , in this case, represents the LV and TV symbols referenced in Table 1 and Table 2.
IN
IN
IN
8.2
FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing
Specifications
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this
section.
8.2.1
FIFO AC Specifications
The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI
specifications, since they have similar performances and are described in a source-synchronous fashion
like FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and
source clock in GMII fashion.
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the
relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,
while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out
onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is
intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a
source- synchronous timing reference. Typically, the clock edge that launched the data can be used, since
the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is
relationship between the maximum FIFO speed and the platform speed. For more information see
Section 4.5, “Platform to FIFO Restrictions.”
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
27
FREESCALE [ Freescale ]
