Enhanced Three-Speed Ethernet (eTSEC)
t
t
FIRR
FIR
RX_CLK
t
t
FIRF
FIRH
RXD[7:0]
RX_DV
RX_ER
Valid Data
t
t
FIRDX
FIRDV
Figure 7. FIFO Receive AC Timing Diagram
8.2.2
GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
8.2.2.1
GMII Transmit AC Timing Specifications
Table 26 provides the GMII transmit AC timing specifications.
Table 26. GMII Transmit AC Timing Specifications
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
GMII data TXD[7:0], TX_ER, TX_EN setup time
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
GTX_CLK data clock rise time (20%–80%)
t
2.5
0.5
—
—
—
—
—
—
ns
ns
ns
ns
GTKHDV
t
5.0
1.0
1.0
GTKHDX
2
t
GTXR
2
GTX_CLK data clock fall time (80%–20%)
t
—
GTXF
Notes:
1. The symbols used for timing specifications follow the pattern t
for inputs
(first two letters of functional block)(signal)(state)(reference)(state)
and t
for outputs. For example, t
symbolizes GMII transmit timing
(first two letters of functional block)(reference)(state)(signal)(state)
GTKHDV
(GT) with respect to the t
clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching
GTX
the valid state (V) to state or setup time. Also, t
symbolizes GMII transmit timing (GT) with respect to the t
clock
GTKHDX
GTX
reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t
represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is
GTX
used with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
29
FREESCALE [ Freescale ]
