DDR and DDR2 SDRAM
6.2.2
DDR SDRAM Output AC Timing Specifications
Table 19. DDR SDRAM Output AC Timing Specifications
At recommended operating conditions.
1
Parameter
Symbol
Min
Max
Unit
Notes
MCK[n] cycle time, MCK[n]/MCK[n] crossing
t
3.75
6
ns
ns
2
3
MCK
ADDR/CMD output setup with respect to MCK
t
t
t
t
DDKHAS
DDKHAX
DDKHCS
DDKHCX
533 MHz
400 MHz
333 MHz
1.48
1.95
2.40
—
—
—
ADDR/CMD output hold with respect to MCK
ns
ns
ns
3
3
3
533 MHz
400 MHz
333 MHz
1.48
1.95
2.40
—
—
—
MCS[n] output setup with respect to MCK
533 MHz
400 MHz
333 MHz
1.48
1.95
2.40
—
—
—
MCS[n] output hold with respect to MCK
533 MHz
400 MHz
333 MHz
1.48
1.95
2.40
—
—
—
MCK to MDQS Skew
t
–0.6
0.6
ns
ps
4
5
DDKHMH
MDQ/MECC/MDM output setup with respect
t
t
t
DDKHDS,
t
DDKLDS
to MDQS
533 MHz
400 MHz
333 MHz
538
700
900
—
—
—
MDQ/MECC/MDM output hold with respect to
MDQS
ps
ns
5
6
DDKHDX,
t
DDKLDX
533 MHz
400 MHz
333 MHz
538
700
900
—
—
—
MDQS preamble start
–0.5 × t
– 0.6
–0.5 × t
+ 0.6
MCK
DDKHMP
MCK
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
22
FREESCALE [ Freescale ]
