DDR and DDR2 SDRAM
6.2
DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface. The DDR
controller supports both DDR1 and DDR2 memories. DDR1 is supported with the following AC timings
at data rates of 333 MHz. DDR2 is supported with the following AC timings at data rates down to
333 MHz.
6.2.1
DDR SDRAM Input AC Timing Specifications
Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
provides the input AC timing specifications for the DDR SDRAM when GV
DD
(typ) = 1.8 V.
At recommended operating conditions
Parameter
AC input low voltage
AC input high voltage
Symbol
V
IL
V
IH
Min
—
MV
REF
+ 0.25
Max
MV
REF
– 0.25
—
Unit
V
V
provides the input AC timing specifications for the DDR SDRAM when GV
DD
(typ) = 2.5 V.
Table 17. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
At recommended operating conditions.
Parameter
AC input low voltage
AC input high voltage
Symbol
V
IL
V
IH
Min
—
MV
REF
+ 0.31
Max
MV
REF
– 0.31
—
Unit
V
V
provides the input AC timing specifications for the DDR SDRAM interface.
Table 18. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions.
Parameter
Controller Skew for MDQS—MDQ/MECC
533 MHz
400 MHz
333 MHz
Symbol
t
CISKEW
Min
Max
Unit
ps
Notes
1, 2
–300
–365
–390
300
365
390
Notes:
1. t
CISKEW
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
will be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t
DISKEW
. This can be
determined by the following equation: t
DISKEW
= ± (T/4 – abs(t
CISKEW
)) where T is the clock period and abs(t
CISKEW
) is the
absolute value of t
CISKEW
.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
21
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
