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MPC8543EVUAQG 参数 Datasheet PDF下载

MPC8543EVUAQG图片预览
型号: MPC8543EVUAQG
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerQUICC ™III集成处理器硬件规格 [PowerQUICC™ III Integrated Processor Hardware Specifications]
分类和应用:
文件页数/大小: 144 页 / 1534 K
品牌: FREESCALE [ Freescale ]
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Clocking  
Table 70. MPC8543E Pinout Listing (continued)  
Power  
Supply  
Signal  
Package Pin Number  
Pin Type  
Notes  
SD_IMP_CAL_TX  
AB26  
I
100 Ω (±1%)  
to GND  
SD_PLL_TPA  
U26  
O
AVDD_SRDS  
24  
Note: All note references in this table use the same numbers as those for Table 67. The reader should refer to Table 67 for the  
meanings of these notes.  
19 Clocking  
This section describes the PLL configuration of the MPC8548E. Note that the platform clock is identical  
to the core complex bus (CCB) clock.  
19.1 Clock Ranges  
Table 71 through Table 73 provide the clocking specifications for the processor cores and Table 74,  
through Table 76 provide the clocking specifications for the memory bus.  
Table 71. Processor Core Clocking Specifications (MPC8548E and MPC8547E)  
Maximum Processor Core Frequency  
Characteristic  
1000 MHz  
1200 MHz  
1333 MHz  
Unit  
Notes  
Min  
800  
Max  
Min  
800  
Max  
Min  
800  
Max  
e500 core processor frequency  
1000  
1200  
1333  
MHz  
1, 2  
Notes:  
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK  
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating  
frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,and Section 19.3, “e500 Core PLL Ratio,for ratio settings.  
2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.  
Table 72. Processor Core Clocking Specifications (MPC8545E)  
Maximum Processor Core Frequency  
Characteristic  
800 MHz  
1000 MHz  
1200 MHz  
Unit  
Notes  
Min  
800  
Max  
Min  
800  
Max  
Min  
800  
Max  
e500 core processor frequency  
800  
1000  
1200  
MHz  
1, 2  
Notes:  
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK  
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating  
frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,and Section 19.3, “e500 Core PLL Ratio,for ratio settings.  
2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.  
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6  
Freescale Semiconductor  
123  
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