I2C
2
13.2 I C AC Electrical Specifications
2
Table 54 provides the AC timing parameters for the I C interfaces.
2
Table 54. I C AC Electrical Specifications
At recommended operating conditions with OVDD of 3.3 V ± 5%. All values refer to VIH (min) and VIL (max) levels (see Table 2).
1
Parameter
Symbol
Min
Max
Unit
4
SCL clock frequency
f
0
400
—
kHz
I2C
Low period of the SCL clock
t
1.3
0.6
0.6
0.6
μs
μs
μs
μs
I2CL
I2CH
High period of the SCL clock
t
—
Setup time for a repeated START condition
t
t
—
I2SVKH
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
t
—
I2SXKL
Data setup time
100
—
ns
I2DVKH
Data input hold time:
t
μs
I2DXKL
I2OVKL
CBUS compatible masters
—
0
—
—
2
2
I C bus devices
3
Data output delay time
t
—
0.6
0.9
μs
μs
μs
V
Setup time for STOP condition
t
—
—
—
I2PVKH
Bus free time between a STOP and START condition
t
1.3
I2KHDX
Noise margin at the LOW level for each connected device
(including hysteresis)
V
0.1 × OV
NL
DD
DD
Noise margin at the HIGH level for each connected device
(including hysteresis)
V
0.2 × OV
—
V
NH
Capacitive load for each bus line
Cb
—
400
pF
Notes:
1.The symbols used for timing specifications herein follow the pattern t
for
(first two letters of functional block)(signal)(state)(reference)(state)
2
inputs and t
for outputs. For example, t
symbolizes I C timing (I2)
(first two letters of functional block)(reference)(state)(signal)(state)
I2DVKH
with respect to the time data input signals (D) reach the valid state (V) relative to the t clock reference (K) going to the high
I2C
2
(H) state or setup time. Also, t
(S) went invalid (X) relative to the t
symbolizes I C timing (I2) for the time that the data with respect to the START condition
clock reference (K) going to the low (L) state or hold time. Also, t
I2SXKL
2
symbolizes I C
I2C
I2PVKH
timing (I2) for the time that the data with respect to the STOP condition (P) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time.
clock
I2C
2. As a transmitter, the MPC8572E provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the
SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP
condition. When the MPC8572E acts as the I2C bus master while transmitting, the MPC8572E drives both SCL and SDA.
As long as the load on SCL and SDA are balanced, the MPC8572E would not cause unintended generation of START or
STOP condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA
output delay time is required for the MPC8572E as transmitter, applicat ion note AN2919 referred to in note 4 below is
recommended.
3.The maximum t
has only to be met if the device does not stretch the LOW period (t
) of the SCL signal.
I2CL
I2OVKL
2
4. The requirements for I C frequency calculation must be followed. Refer to Freescale application note AN2919, Determining
2
the I C Frequency Divider Ratio for SCL.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
68
Freescale Semiconductor
FREESCALE [ Freescale ]
