Programmable Interrupt Controller
11 Programmable Interrupt Controller
In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed
polarity), it must remain asserted for at least 3 system clocks (SYSCLK periods).
12 JTAG
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the
MPC8572E.
Table 52 provides the JTAG AC timing specifications as defined in Figure 37 through Figure 39.
1
Table 52. JTAG AC Timing Specifications (Independent of SYSCLK)
At recommended operating conditions with OVDD of 3.3 V ± 5%.
2
Parameter
Symbol
Min
Max
Unit
Notes
JTAG external clock frequency of operation
JTAG external clock cycle time
f
0
33.3
—
MHz
ns
—
—
—
6
JTG
t
30
15
0
JTG
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
t
—
ns
JTKHKL
t
& t
2
ns
JTGR
JTGF
t
25
—
ns
3
TRST
Input setup times:
Boundary-scan data
TMS, TDI
ns
t
t
4
0
—
—
4
4
5
5
JTDVKH
JTIVKH
Input hold times:
Boundary-scan data
TMS, TDI
ns
ns
ns
t
20
25
—
—
JTDXKH
t
JTIXKH
Valid times:
Boundary-scan data
TDO
t
t
4
4
20
25
JTKLDV
JTKLOV
Output hold times:
Boundary-scan data
TDO
t
t
30
30
—
—
JTKLDX
JTKLOX
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
65
FREESCALE [ Freescale ]
