JTAG
1
Table 52. JTAG AC Timing Specifications (Independent of SYSCLK) (continued)
At recommended operating conditions with OVDD of 3.3 V ± 5%.
2
Parameter
Symbol
Min
Max
Unit
Notes
JTAG external clock to output high impedance:
ns
Boundary-scan data
TDO
t
t
3
3
19
9
5, 6
JTKLDZ
JTKLOZ
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
to the midpoint of the signal in question.
TCLK
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 36).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes JTAG
(first two letters of functional block)(reference)(state)(signal)(state)
JTDVKH
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
clock reference
JTG
(K) going to the high (H) state or setup time. Also, t
symbolizes JTAG timing (JT) with respect to the time data input
JTDXKH
signals (D) went invalid (X) relative to the t
clock reference (K) going to the high (H) state. Note that, in general, the clock
JTG
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
.
TCLK
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design.
.
TCLK
Figure 36 provides the AC test load for TDO and the boundary-scan outputs.
Z = 50 Ω
OV /2
Output
0
DD
R = 50 Ω
L
Figure 36. AC Test Load for the JTAG Interface
Figure 37 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
VM
VM
t
t
JTKHKL
JTGR
t
t
JTGF
JTG
VM = Midpoint Voltage (OV /2)
DD
Figure 37. JTAG Clock Input Timing Diagram
Figure 38 provides the TRST timing diagram.
TRST
VM
VM
t
TRST
VM = Midpoint Voltage (OV /2)
DD
Figure 38. TRST Timing Diagram
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
66
FREESCALE [ Freescale ]
