I2C
Figure 39 provides the boundary-scan timing diagram.
JTAG
VM
VM
External Clock
t
JTDVKH
t
JTDXKH
Boundary
Data Inputs
Input
Data Valid
t
JTKLDV
t
JTKLDX
Boundary
Data Outputs
Output Data Valid
t
JTKLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OV /2)
DD
Figure 39. Boundary-Scan Timing Diagram
13 I2C
2
This section describes the DC and AC electrical characteristics for the I C interfaces of the MPC8572E.
2
13.1 I C DC Electrical Characteristics
2
Table 53 provides the DC electrical characteristics for the I C interfaces.
2
Table 53. I C DC Electrical Characteristics
Parameter
Input high voltage level
Symbol
Min
Max
Unit
Notes
V
0.7 × OV
OV + 0.3
V
V
—
—
1
IH
DD
DD
Input low voltage level
Low level output voltage
V
–0.3
0
0.3 × OV
IL
DD
V
0.4
50
V
OL
Pulse width of spikes which must be suppressed by the
input filter
t
0
ns
2
I2KHKL
Input current each I/O pin (input voltage is between
I
–10
—
10
10
μA
3
I
0.1 × OV and 0.9 × OV (max)
DD
DD
Capacitance for each I/O pin
C
pF
—
I
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. Refer to the MPC8572E PowerQUICC™ III Integrated Host Processor Family Reference Manual for information on the digital
filter used.
3. I/O pins will obstruct the SDA and SCL lines if OV is switched off.
DD
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
67
FREESCALE [ Freescale ]
