Local Bus Controller (eLBC)
Figure 30 through Figure 35 show the local bus signals.
LSYNC_IN
t
LBIXKH1
t
t
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBIXKH2
LBIVKH2
Input Signal:
LGTA/LFRB
LUPWAIT
t
LBKHOZ1
LBKHOX1
t
t
t
LBKHOV1
Output Signals:
LA[27:31]/LCS[0:7]/LWE[0:3]/
LFWE/LBCTL/LFCLE/
LFALE/LOE/LFRE/LFWP
t
LBKHOZ2
LBKHOX2
t
LBKHOV2
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ2
LBKHOX2
t
t
LBKHOV3
Output (Address) Signal:
LAD[0:31]
t
LBOTOT
t
LBKHOV4
LALE
Figure 30. Local Bus Signals, Non-Special Signals Only (PLL Enabled)
Table 51 describes the general timing parameters of the local bus interface at BV = 3.3 V DC with PLL
DD
disabled.
Table 51. Local Bus General Timing Parameters—PLL Bypassed
At recommended operating conditions with BVDD of 3.3 V ± 5%
1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus cycle time
Local bus duty cycle
t
12
43
—
57
4.0
—
ns
%
2
—
LBK
t
t
LBKH/ LBK
Internal launch/capture clock to LCLK delay
t
2.3
5.8
ns
ns
—
LBKHKT
Input setup to local bus clock (except
LGTA/LUPWAIT)
t
4, 5
LBIVKH1
LGTA/LUPWAIT input setup to local bus clock
t
5.7
—
—
ns
ns
4, 5
4, 5
LBIVKL2
Input hold from local bus clock (except
LGTA/LUPWAIT)
t
-1.3
LBIXKH1
LGTA/LUPWAIT input hold from local bus clock
t
-1.3
—
ns
4, 5
LBIXKL2
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
58
FREESCALE [ Freescale ]
