Local Bus Controller (eLBC)
Table 51. Local Bus General Timing Parameters—PLL Bypassed (continued)
At recommended operating conditions with BVDD of 3.3 V ± 5%
1
Parameter
Symbol
Min
Max
Unit
Notes
LALE output negation to high impedance for
LAD/LDP (LATCH hold time)
t
1.5
—
ns
6
LBOTOT
Local bus clock to output valid (except LAD/LDP and
LALE)
t
—
–0.3
ns
LBKLOV1
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
t
t
t
t
—
—
–0.1
0.0
0.0
—
ns
ns
ns
ns
4
4
4
4
LBKLOV2
LBKLOV3
LBKLOV4
LBKLOX1
—
Output hold from local bus clock (except LAD/LDP
and LALE)
–3.3
Output hold from local bus clock for LAD/LDP
t
t
–3.3
—
—
ns
ns
4
7
LBKLOX2
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
0.2
LBKLOZ1
Local bus clock to output high impedance for
LAD/LDP
t
—
0.2
ns
7
LBKLOZ2
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes local bus
(First two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this case for
LBK
clock one(1). Also, t
symbolizes local bus timing (LB) for the t
clock reference (K) to go high (H), with respect to the
LBKHOX
LBK
output (O) going invalid (X) or output hold time.
2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus
clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes LCLK
by t
.
LBKHKT
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BV /2.
DD
4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal
in question for 3.3-V signaling levels.
5. Input timings are measured at the pin.
6. t
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
is
LBOTOT
LBOTOT
programmed with the LBCR[AHD] parameter.
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
NOTE
In PLL bypass mode, LCLK[n] is the inverted version of the internal clock
with the delay of tLBKHKT. In this mode, signals are launched at the rising edge
of the internal clock and are captured at the falling edge of the internal clock
with the exception of LGTA/LUPWAIT (which is captured on the rising
edge of the internal clock).
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
59
FREESCALE [ Freescale ]
