Local Bus Controller (eLBC)
Table 48. Local Bus General Timing Parameters (BV = 3.3 V DC)—PLL Enabled (continued)
DD
At recommended operating conditions with BVDD of 3.3 V ± 5%. (continued)
1
Parameter
Symbol
Min
Max
Unit
Notes
Output hold from local bus clock (except LAD/LDP and
LALE)
t
0.7
—
ns
3
LBKHOX1
Output hold from local bus clock for LAD/LDP
t
t
0.7
—
—
ns
ns
3
5
LBKHOX2
Local bus clock to output high Impedance (except LAD/LDP
and LALE)
2.5
LBKHOZ1
Local bus clock to output high impedance for LAD/LDP
t
—
2.5
ns
5
LBKHOZ2
Note:
1. The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example,
(reference)(state)
(First two letters of functional block)(reference)(state)(signal)(state)
t
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock
LBIXKH1
LBK
reference (K) goes high (H), in this case for clock one(1). Also, t
symbolizes local bus timing (LB) for the
LBKHOX
t
clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.
LBK
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV /2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock
DD
for PLL bypass mode to 0.4 × BV of the signal in question for 3.3-V signaling levels.
DD
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
6. t
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
is
LBOTOT
LBOTOT
programmed with the LBCR[AHD] parameter.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BV /2.
DD
8. Guaranteed by design.
Table 49 describes the general timing parameters of the local bus interface at BV = 2.5 V DC.
DD
Table 49. Local Bus General Timing Parameters (BV = 2.5 V DC)—PLL Enabled
DD
At recommended operating conditions with BVDD of 2.5 V ± 5%
Parameter
1
Symbol
Min
Max
Unit
Notes
Local bus cycle time
Local bus duty cycle
t
6.67
43
12
57
150
—
ns
%
2
LBK
t
t
—
LBKH/ LBK
LCLK[n] skew to LCLK[m] or LSYNC_OUT
t
—
ps
ns
ns
ns
7, 8
3, 4
3, 4
3, 4
LBKSKEW
Input setup to local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input setup to local bus clock
t
t
t
1.9
1.8
1.1
LBIVKH1
LBIVKH2
LBIXKH1
—
Input hold from local bus clock (except
LGTA/LUPWAIT)
—
LGTA/LUPWAIT input hold from local bus clock
t
1.1
1.5
—
—
ns
ns
3, 4
6
LBIXKH2
LALE output negation to high impedance for LAD/LDP
(LATCH hold time)
t
LBOTOT
Local bus clock to output valid (except LAD/LDP and
LALE)
t
—
2.4
ns
—
LBKHOV1
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
55
FREESCALE [ Freescale ]
