Local Bus Controller (eLBC)
Internal launch/
capture clock
t
LBKHKT
LCLK[n]
t
LBIVKH1
t
LBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBIVKL2
Input Signal:
LGTA/LFRB
t
LBIXKL2
LUPWAIT
t
LBKLOV1
t
LBKLOZ1
LBKLOZ2
t
LBKLOX1
Output Signals:
LA[27:31]/LCS[0:7]/
LWE[0:3]/LFWE/
LBCTL/LFCLE/LFALE/
LOE/LFRE/LFWP
t
t
LBKLOV2
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
t
LBKLOX2
LBKLOV3
Output (Address) Signal:
LAD[0:31]
t
t
LBKLOV4
LBOTOT
LALE
Figure 31. Local Bus Signals (PLL Bypass Mode)
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
60