Local Bus Controller (eLBC)
Table 47 provides the DC electrical characteristics for the local bus interface operating at BV = 1.8 V
DD
DC.
Table 47. Local Bus DC Electrical Characteristics (1.8 V DC)
Parameter
Supply voltage 1.8V
Symbol
Min
Max
Unit
BV
1.71
0.65 x BV
–0.3
1.89
V
V
DD
High-level input voltage
Low-level input voltage
V
BV + 0.3
DD
IH
DD
V
0.35 x BV
TBD
V
IL
DD
Input current
I
TBD
μA
IN
1
(BV
= 0 V or BV = BV
)
DD
IN
IN
High-level output voltage
V
V
BV – 0.2
—
—
V
V
V
V
OH
DD
(I = –100 μA)
OH
High-level output voltage
BV – 0.45
OH
DD
(I = –2 mA)
OH
Low-level output voltage
V
—
—
0.2
0.45
OL
(I = 100 μA)
OL
Low-level output voltage
V
OL
(I = 2 mA)
OL
Note:
1. The symbol BV , in this case, represents the BV symbol referenced in Table 1.
IN
IN
10.2 Local Bus AC Electrical Specifications
Table 48 describes the general timing parameters of the local bus interface at BV = 3.3 V DC.
DD
Table 48. Local Bus General Timing Parameters (BV = 3.3 V DC)—PLL Enabled
DD
At recommended operating conditions with BVDD of 3.3 V ± 5%.
Parameter
1
Symbol
Min
Max
Unit
Notes
Local bus cycle time
Local bus duty cycle
t
6.67
43
12
57
150
—
ns
%
2
LBK
t
t
—
LBKH/ LBK
LCLK[n] skew to LCLK[m] or LSYNC_OUT
t
—
ps
ns
ns
ns
ns
ns
7,8
3, 4
3, 4
3, 4
3, 4
6
LBKSKEW
Input setup to local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input setup to local bus clock
Input hold from local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input hold from local bus clock
t
t
t
t
1.8
1.7
1.0
1.0
1.5
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
—
—
—
LALE output negation to high impedance for LAD/LDP
(LATCH hold time)
t
—
LBOTOT
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
t
—
—
—
—
2.3
2.4
2.3
2.3
ns
ns
ns
ns
—
3
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOV4
t
t
t
3
3
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
54
FREESCALE [ Freescale ]
