Clocking
Note that the DDR PLL reference clock input, DDRCLK, is only required in asynchronous mode.
MPC8572E does not support running one DDR controller in synchronous mode and the other in
asynchronous mode.
Table 81. DDR Clock Ratio
Binary Value of
TSEC_1588_CLK_OUT,
DDR:DDRCLK Ratio
TSEC_1588_PULSE_OUT1,
TSEC_1588_PULSE_OUT2 Signals
000
001
010
011
100
101
110
111
3:1
4:1
6:1
8:1
10:1
12:1
14:1
Synchronous mode
19.5 Frequency Options
19.5.1 Platform to Sysclk Frequency Options
Table 82 shows the expected frequency values for the platform frequency when using the specified CCB
clock to SYSCLK ratio.
Table 82. Frequency Options for Platform Frequency
CCB to
SYSCLK (MHz)
SYSCLK Ratio
33.33
41.66
50
66.66
83
100
111
133.33
Platform /CCB Frequency (MHz)
400
4
5
444
555
533
415
498
500
600
6
400
533
8
400
500
600
10
12
417
500
400
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
121
FREESCALE [ Freescale ]
