欢迎访问ic37.com |
会员登录 免费注册
发布采购

MPC8572ELVTAULD 参数 Datasheet PDF下载

MPC8572ELVTAULD图片预览
型号: MPC8572ELVTAULD
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8572E的PowerQUICC III集成处理器硬件规格 [MPC8572E PowerQUICC III Integrated Processor Hardware Specifications]
分类和应用: PC
文件页数/大小: 140 页 / 1412 K
品牌: FREESCALE [ Freescale ]
 浏览型号MPC8572ELVTAULD的Datasheet PDF文件第116页浏览型号MPC8572ELVTAULD的Datasheet PDF文件第117页浏览型号MPC8572ELVTAULD的Datasheet PDF文件第118页浏览型号MPC8572ELVTAULD的Datasheet PDF文件第119页浏览型号MPC8572ELVTAULD的Datasheet PDF文件第121页浏览型号MPC8572ELVTAULD的Datasheet PDF文件第122页浏览型号MPC8572ELVTAULD的Datasheet PDF文件第123页浏览型号MPC8572ELVTAULD的Datasheet PDF文件第124页  
Clocking  
Table 79 describes the clock ratio between e500 Core0 and the e500 core complex bus (CCB). This ratio  
is determined by the binary value of LBCTL, LALE and LGPL2/LOE/LFRE at power up, as shown in  
Table 79.  
Table 79. e500 Core0 to CCB Clock Ratio  
Binary Value of  
LBCTL, LALE,  
LGPL2/LOE/LFRE  
Signals  
Binary Value of  
LBCTL, LALE,  
LGPL2/LOE/LFRE  
Signals  
e500 Core0:CCB Clock Ratio  
e500 Core0:CCB Clock Ratio  
000  
001  
010  
011  
Reserved  
Reserved  
Reserved  
3:2 (1.5:1)  
100  
101  
110  
111  
2:1  
5:2 (2.5:1)  
3:1  
7:2 (3.5:1)  
Table 80 describes the clock ratio between e500 Core1 and the e500 core complex bus (CCB). This ratio  
is determined by the binary value of LWE[0]/LBS[0]/LFWE, UART_SOUT[1], and READY_P1 signals  
at power up, as shown in Table 80.  
Table 80. e500 Core1 to CCB Clock Ratio  
Binary Value of  
LWE[0]/LBS[0]/  
LFWE, UART_SOUT[1],  
READY_P1 Signals  
Binary Value of  
LWE[0]/LBS[0]/  
LFWE, UART_SOUT[1],  
READY_P1 Signals  
e500 Core1:CCB Clock Ratio  
e500 Core1:CCB Clock Ratio  
000  
001  
010  
011  
Reserved  
Reserved  
Reserved  
3:2 (1.5:1)  
100  
101  
110  
111  
2:1  
5:2 (2.5:1)  
3:1  
7:2 (3.5:1)  
19.4 DDR/DDRCLK PLL Ratio  
The dual DDR memory controller complexes can be synchronous with, or asynchronous to, the CCB,  
depending on configuration.  
Table 81 describes the clock ratio between the DDR memory controller complexes and the DDR PLL  
reference clock, DDRCLK, which is not the memory bus clock. The DDR memory controller complexes  
clock frequency is equal to the DDR data rate.  
When synchronous mode is selected, the memory buses are clocked at half the CCB clock rate. The default  
mode of operation is for the DDR data rate for both DDR controllers to be equal to the CCB clock rate in  
synchronous mode, or the resulting DDR PLL rate in asynchronous mode.  
In asynchronous mode, the DDR PLL rate to DDRCLK ratios listed in Table 81 reflects the DDR data rate  
to DDRCLK ratio, because the DDR PLL rate in asynchronous mode means the DDR data rate resulting  
from DDR PLL output.  
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4  
120  
Freescale Semiconductor  
 复制成功!