欢迎访问ic37.com |
会员登录 免费注册
发布采购

MPC8572ELVTAULD 参数 Datasheet PDF下载

MPC8572ELVTAULD图片预览
型号: MPC8572ELVTAULD
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8572E的PowerQUICC III集成处理器硬件规格 [MPC8572E PowerQUICC III Integrated Processor Hardware Specifications]
分类和应用: PC
文件页数/大小: 140 页 / 1412 K
品牌: FREESCALE [ Freescale ]
 浏览型号MPC8572ELVTAULD的Datasheet PDF文件第115页浏览型号MPC8572ELVTAULD的Datasheet PDF文件第116页浏览型号MPC8572ELVTAULD的Datasheet PDF文件第117页浏览型号MPC8572ELVTAULD的Datasheet PDF文件第118页浏览型号MPC8572ELVTAULD的Datasheet PDF文件第120页浏览型号MPC8572ELVTAULD的Datasheet PDF文件第121页浏览型号MPC8572ELVTAULD的Datasheet PDF文件第122页浏览型号MPC8572ELVTAULD的Datasheet PDF文件第123页  
Clocking  
As a general guideline when selecting the DDR data rate or platform (CCB) frequency, the following  
procedures can be used:  
Start with the processor core frequency selection;  
After the processor core frequency is determined, select the platform (CCB) frequency from the  
limited options listed in Table 79 and Table 80;  
Check the CCB to SYSCLK ratio to verify a valid ratio can be choose from Table 78;  
If the desired DDR data rate can be same as the CCB frequency, use the synchronous DDR mode;  
Otherwise, if a higher DDR data rate is desired, use asynchronous mode by selecting a valid DDR  
data rate to DDRCLK ratio from Table 81. Note that in asynchronous mode, the DDR data rate  
must be greater than the platform (CCB) frequency. In other words, running DDR data rate lower  
than the platform (CCB) frequency in asynchronous mode is not supported by MPC8572E.  
Verify all clock ratios to ensure that there is no violation to any clock and/or ratio specification.  
19.2 CCB/SYSCLK PLL Ratio  
The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform  
clock. The frequency of the CCB is set using the following reset signals, as shown in Table 78:  
SYSCLK input signal  
Binary value on LA[29:31] at power up  
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note  
that, in synchronous mode, the DDR data rate is the determining factor in selecting the CCB bus frequency,  
because the CCB frequency must equal the DDR data rate. In asynchronous mode, the memory bus clock  
frequency is decoupled from the CCB bus frequency.  
Table 78. CCB Clock Ratio  
Binary Value of  
CCB:SYSCLK Ratio  
LA[29:31] Signals  
000  
001  
010  
011  
100  
101  
110  
111  
4:1  
5:1  
6:1  
8:1  
10:1  
12:1  
Reserved  
Reserved  
19.3 e500 Core PLL Ratio  
The clock speed for each e500 core can be configured differently, determined by the values of various  
signals at power up.  
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4  
Freescale Semiconductor  
119