Clocking
19 Clocking
This section describes the PLL configuration of the MPC8572E. Note that the platform clock is identical
to the core complex bus (CCB) clock.
19.1 Clock Ranges
Table 76 provides the clocking specifications for both processor cores.
Table 76. MPC8572E Processor Core Clocking Specifications
Maximum Processor Core Frequency
Characteristic
1067 MHz
1200 MHz
1333 MHz
1500 MHz
Min Max
1500 MHz
Unit Notes
Min
Max
Min
Max
Min
Max
e500 core processor frequency
CCB frequency
800
400
400
1067
533
800
400
400
1200
533
800
400
400
1333
533
800
400
400
1, 2
600
800
MHz
MHz
DDR Data Rate
667
667
667
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” Section 19.3, “e500 Core PLL Ratio,” and Section 19.4,
“DDR/DDRCLK PLL Ratio,” for ratio settings.
2. The processor core frequency speed bins listed also reflect the maximum platform (CCB) and DDR data rate frequency
supported by production test. Running CCB and/or DDR data rate higher than the limit shown above, although logically
possible via valid clock ratio setting in some condition, is not supported.
The DDR memory controller can run in either synchronous or asynchronous mode. When running in
synchronous mode, the memory bus is clocked relative to the platform clock frequency. When running in
asynchronous mode, the memory bus is clocked with its own dedicated PLL with clock provided on
DDRCLK input pin. Table 77 provides the clocking specifications for the memory bus.
Table 77. Memory Bus Clocking Specifications
Characteristic
Min
Max
Unit
Notes
Memory bus clock frequency
Notes:
200
400
MHz
1, 2, 3, 4
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” Section 19.3, “e500 Core PLL Ratio,” and
Section 19.4, “DDR/DDRCLK PLL Ratio,” for ratio settings.
2. The Memory bus clock refers to the MPC8572E memory controllers’ Dn_MCK[0:5] and Dn_MCK[0:5] output clocks, running
at half of the DDR data rate.
3. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is
the same as the platform (CCB) frequency. If the desired DDR data rate is higher than the platform (CCB) frequency,
asynchronous mode must be used.
4. In asynchronous mode, the memory bus clock speed is dictated by its own PLL. Refer to Section 19.4, “DDR/DDRCLK PLL
Ratio.” The memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the
DDR data rate.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
118
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