RapidIO
13.3.2 RapidIO Receiver AC Timing Specifications
The RapidIO receiver AC timing specifications are provided in
A receiver shall comply with the
specifications for each data rate/frequency for which operation of the receiver is specified. Unless
otherwise specified, these specifications are subject to the following conditions.
• The specifications apply over the supply voltage and ambient temperature ranges specified by the
device vendor.
• The specifications apply for any combination of data patterns on the data signals.
• The specifications apply over the receiver common mode and differential input voltage ranges.
• Clock specifications apply only to clock signals.
• Data specifications apply only to data signals (FRAME, D[0:7])
Table 50. RapidIO Receiver AC Timing Specifications—500 Mbps Data Rate
Range
Characteristic
Symbol
Min
Duty cycle of the clock input
Data valid
Allowable static skew between any two data inputs
within a 8-/9-bit group
Allowable static skew of data inputs to associated clock
DC
DV
t
DPAIR
t
SKEW,PAIR
47
1080
—
–300
380
300
Max
53
%
ps
ps
ps
1, 5
2
3
4
Unit
Notes
Notes:
1.Measured at V
ID
= 0 V.
2.Measured using the RapidIO receive mask shown in
3.See
4.See
and
5.Guaranteed by design.
Table 51. RapidIO Receiver AC Timing Specifications—750 Mbps Data Rate
Range
Characteristic
Symbol
Min
Duty cycle of the clock input
Data valid
Allowable static skew between any two data inputs
within a 8-/9-bit group
Allowable static skew of data inputs to associated clock
DC
DV
t
DPAIR
t
SKEW,PAIR
47
600
—
–267
Max
53
—
400
267
%
ps
ps
ps
1, 5
2
3
4
Unit
Notes
Notes:
1.Measured at V
ID
= 0 V.
2.Measured using the RapidIO receive mask shown in
3.See
4.See
and
5.Guaranteed by design.
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
62
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
