RapidIO
Figure 41 shows the definitions of the data to clock static skew parameter t
and the data valid
SKEW,PAIR
window parameter DV. The data and frame bits are those that are associated with the clock. The figure
applies for all zero-crossings of the clock. All of the signals are differential signals. V represents V for
D
OD
the transmitter and V for the receiver. The center of the eye is defined as the midpoint of the region in
ID
which the magnitude of the signal voltage is greater than or equal to the minimum DV voltage.
VD Clock x
VD Clock x
VD = 0 V
VD = 0 V
1.0 UI Nominal
0.5 UI
tSKEW,PAIR
0.5 DV
Eye Opening
DV
Figure 41. Data to Clock Skew
0.5 DV
VHDmim
D[0:7]/D[8:15], FRAME
VHDmim
Figure 42 shows the definition of the data to data static skew parameter t
parameters are applied.
and how the skew
DPAIR
1.0 UI Nominal
0.5 UI
Center Point for Clock
CLK0 (CLK1)
Center point of the
data valid window of
the earliest allowed data
bit for data grouped
late with respect
to clock
Center point of the
data valid window of
the latest allowed data
bit for data grouped
late with respect
to clock
D[0:7]/D[8:15], FRAME
tDPAIR
tSKEW,PAIR
Figure 42. Static Skew Diagram
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
65
FREESCALE [ Freescale ]
