Ordering Information
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V
1
= R
source
×
I
source
. Second, the output voltage is measured
while driving logic 1 with an external precision differential termination resistor of value R
term
. The
measured voltage is V
2
= (1/(1/R
1
+ 1/R
2
))
×
I
source
. Solving for the output impedance gives R
source
=
R
term
×
(V
1
/V
2
– 1). The drive current is then I
source
= V
1
/R
source
.
summarizes the signal impedance targets. The driver impedance are targeted at minimum V
DD
,
nominal OV
DD
, 105°C.
Table 78. Impedance Characteristics
Local Bus, Ethernet,
DUART, Control,
Configuration, Power
Management
42 Target
42 Target
NA
PCI Signals
(not including PCI
output clocks)
25 Target
25 Target
NA
PCI Output Clocks
(including
PCI_SYNC_OUT)
42 Target
42 Target
NA
Impedance
DDR DRAM
Symbol
Unit
R
N
R
P
Differential
20 Target
20 Target
NA
Z
0
Z
0
Z
DIFF
W
W
W
Note:
Nominal supply voltages. See
T
j
= 105°C.
24.5
Configuration Pin Muxing
The device provides the user with power-on configuration options which can be set through the use of
external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration
pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when PORESET deasserts, at which time the input receiver is
disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections
to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should
minimize the disruption of signal quality or speed for output pins thus configured.
24.6
Pull-Up Resistor Requirements
The device requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins
including I
2
C pins, Ethernet Management MDIO pin and IPIC interrupt pins.
For more information on required pull-up resistors and the connections required for the JTAG interface,
see AN3665, “MPC837xE Design Checklist.”
25 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in
MPC8378E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
121
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
