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MPC8378ECVRALGA 参数 Datasheet PDF下载

MPC8378ECVRALGA图片预览
型号: MPC8378ECVRALGA
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerQUICC ™II Pro处理器硬件规格 [PowerQUICC™ II Pro Processor Hardware Specifications]
分类和应用: 外围集成电路时钟
文件页数/大小: 126 页 / 1421 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
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System Design Information
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
24.3
Connection Recommendations
To ensure reliable operation, it is highly recommended that unused inputs be connected to an appropriate
signal level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused
active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins
of the device.
24.4
Output Buffer DC Impedance
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a
push-pull single-ended driver type (open drain for I
2
C).
To measure Z
0
for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
or GND. Then, the value of each resistor is varied until the pad voltage is OV
DD
/2 (see
The
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R
P
is trimmed until the voltage at the pad equals
OV
DD
/2. R
P
then becomes the resistance of the pull-up devices. R
P
and R
N
are designed to be close to each
other in value. Then, Z
0
= (R
P
+ R
N
)/2.
OVDD
R
N
SW2
Data
Pad
SW1
R
P
OGND
Figure 69. Driver Impedance Measurement
MPC8378E PowerQUICC
II Pro Processor Hardware Specifications, Rev. 2
120
Freescale Semiconductor