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MPC8347ECVVAGDB 参数 Datasheet PDF下载

MPC8347ECVVAGDB图片预览
型号: MPC8347ECVVAGDB
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8347EA的PowerQUICC II Pro整合型主机处理器的硬件规格 [MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications]
分类和应用: 外围集成电路PC时钟
文件页数/大小: 99 页 / 727 K
品牌: FREESCALE [ Freescale ]
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Overview  
— Can operate as a stand-alone USB host controller  
– USB root hub with one downstream-facing port  
– Enhanced host controller interface (EHCI) compatible  
– High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations  
— External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)  
Universal serial bus (USB) multi-port host controller  
— Can operate as a stand-alone USB host controller  
– USB root hub with one or two downstream-facing ports  
– Enhanced host controller interface (EHCI) compatible  
– Complies with USB Specification Rev. 2.0  
— High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations  
— Direct connection to a high-speed device without an external hub  
— External PHY with serial and low-pin count (ULPI) interfaces  
Local bus controller (LBC)  
— Multiplexed 32-bit address and data operating at up to 133 MHz  
— Eight chip selects for eight external slaves  
— Up to eight-beat burst transfers  
— 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller  
— Three protocol engines on a per chip select basis:  
– General-purpose chip select machine (GPCM)  
– Three user-programmable machines (UPMs)  
– Dedicated single data rate SDRAM controller  
— Parity support  
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)  
Programmable interrupt controller (PIC)  
— Functional and programming compatibility with the MPC8260 interrupt controller  
— Support for 8 external and 35 internal discrete interrupt sources  
— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources  
— Programmable highest priority request  
— Four groups of interrupts with programmable priority  
— External and internal interrupts directed to host processor  
— Redirects interrupts to external INTA pin in core disable mode.  
— Unique vector number for each interrupt source  
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Dual industry-standard I C interfaces  
— Two-wire interface  
— Multiple master support  
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— Master or slave I C mode support  
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12  
Freescale Semiconductor  
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