Electrical Characteristics
— On-chip digital filtering rejects spikes on the bus
2
— System initialization data optionally loaded from I C-1 EPROM by boot sequencer embedded
hardware
•
DMA controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— Handshaking (external control) signals for all channels: DMA_DREQ[0:3],
DMA_DACK[0:3], DMA_DDONE[0:3]
— All channels accessible to local core and remote PCI masters
— Misaligned transfer capability
— Data chaining and direct mode
— Interrupt on completed segment and chain
DUART
•
— Two 4-wire interfaces (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
Serial peripheral interface (SPI) for master or slave
General-purpose parallel I/O (GPIO)
•
•
— 52 parallel I/O pins multiplexed on various chip interfaces
System timers
•
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Eight general-purpose timers
•
•
Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan
Integrated PCI bus and SDRAM clock generation
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8347EA. The device is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
6
Freescale Semiconductor
FREESCALE [ Freescale ]
