Peripheral operating requirements and behaviors
Table 26. SPI slave mode timing on slew rate enabled pads (continued)
Num.
2
Symbol Description
Min.
Max.
—
Unit
ns
Note
2
tSPSCK
tLead
tLag
SPSCK period
Enable lead time
Enable lag time
4 x tperiph
3
1
—
tperiph
tperiph
ns
—
—
—
—
—
3
4
1
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2
7
—
ns
7
—
ns
8
—
—
—
0
tperiph
tperiph
122
—
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
ns
—
tperiph - 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
36
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL 0)
=
(INPUT)
5
5
3
SPSCK
=
(CPOL 1)
(INPUT)
9
8
10
11
11
MISO
(OUTPUT)
see
SEE
BIT 6 . . . 1
SLAVE LSB OUT
SLAVE MSB
7
note
NOTE
6
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE: Not defined!
Figure 11. SPI slave mode timing (CPHA = 0)
KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
39
FREESCALE [ Freescale ]
