Peripheral operating requirements and behaviors
6.8.3 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. See the SPI chapter of the
chip's Reference Manual for information about the modified transfer formats used for
communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as
well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 23. SPI master mode timing on slew rate disabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
16
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
10
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph - 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
Table 24. SPI master mode timing on slew rate enabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
6
tSU
Data setup time (inputs)
Table continues on the next page...
96
—
ns
—
KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
36
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
