Peripheral operating requirements and behaviors
Table 24. SPI master mode timing on slew rate enabled pads (continued)
Num.
Symbol Description
Min.
0
Max.
Unit
ns
Note
—
7
8
tHI
tv
Data hold time (inputs)
—
52
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
—
0
ns
—
9
tHO
tRI
—
ns
—
10
—
tperiph - 25
ns
—
tFI
Fall time input
11
tRO
tFO
Rise time output
—
36
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
5
=
(CPOL 0)
(OUTPUT)
5
SPSCK
(CPOL 1)
=
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
LSB OUT
MSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 9. SPI master mode timing (CPHA = 0)
KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
37
FREESCALE [ Freescale ]
