Pinout
8 Pinout
8.1 KL24 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
80
64
48
32
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP
QFN
QFN
1
2
1
2
—
—
—
—
—
—
1
1
—
—
—
—
—
—
2
PTE0
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
VDD
PTE0
UART1_TX
UART1_RX
RTC_CLKOUT CMP0_OUT
SPI1_MISO
I2C1_SDA
I2C1_SCL
PTE1
PTE1
PTE2
PTE3
PTE4
PTE5
SPI1_MOSI
SPI1_SCK
SPI1_MISO
SPI1_PCS0
3
—
—
—
—
3
PTE2
4
PTE3
SPI1_MOSI
5
PTE4
6
PTE5
7
VDD
VDD
VSS
8
4
2
VSS
VSS
9
5
3
3
USB0_DP
USB0_DM
VOUT33
VREGIN
PTE20
PTE21
PTE22
PTE23
VDDA
VREFH
VREFL
VSSA
USB0_DP
USB0_DM
VOUT33
VREGIN
USB0_DP
USB0_DM
VOUT33
VREGIN
10
11
12
13
14
15
16
17
18
19
20
21
6
4
4
7
5
5
8
6
6
9
7
—
—
—
—
7
ADC0_SE0
ADC0_SE4a
ADC0_SE3
ADC0_SE7a
VDDA
ADC0_SE0
ADC0_SE4a
ADC0_SE3
ADC0_SE7a
VDDA
PTE20
PTE21
PTE22
PTE23
TPM1_CH0
TPM1_CH1
TPM2_CH0
TPM2_CH1
UART0_TX
UART0_RX
UART2_TX
UART2_RX
10
11
12
13
14
15
16
17
8
—
—
9
10
11
12
13
—
—
8
VREFH
VREFH
VREFL
VREFL
VSSA
VSSA
—
PTE29
CMP0_IN5/
ADC0_SE4b
CMP0_IN5/
ADC0_SE4b
PTE29
PTE30
TPM0_CH2
TPM0_CH3
TPM_CLKIN0
TPM_CLKIN1
22
18
14
9
PTE30
ADC0_SE23/
CMP0_IN4
ADC0_SE23/
CMP0_IN4
23
24
25
26
27
28
19
20
21
22
23
24
—
15
16
17
18
19
—
—
—
10
11
12
PTE31
PTE24
PTE25
PTA0
DISABLED
DISABLED
DISABLED
SWD_CLK
DISABLED
DISABLED
PTE31
PTE24
PTE25
PTA0
TPM0_CH4
TPM0_CH0
TPM0_CH1
TPM0_CH5
TPM2_CH0
TPM2_CH1
I2C0_SCL
I2C0_SDA
SWD_CLK
PTA1
PTA1
UART0_RX
UART0_TX
PTA2
PTA2
KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
41
FREESCALE [ Freescale ]
