Thermal specifications
5.3 Thermal specifications
5.3.1 Thermal characteristics
This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-
determined rather than being controlled by the MCU design. To take PI/O into account in
power calculations, determine the difference between actual pin voltage and VSS or VDD
and multiply by the pin current for each I/O pin. Except in cases of unusually high pin
current (heavy loads), the difference between pin voltage and VSS or VDD will be very
small.
Table 8. Thermal attributes
Board type
Symbol
Description
64
64 QFP
44
32
Unit
Notes
LQFP
LQFP
LQFP
Single-layer (1S)
RθJA
Thermal resistance, junction
to ambient (natural
convection)
71
53
59
46
61
75
53
62
47
86
57
72
51
°C/W
1, 2
Four-layer (2s2p)
Single-layer (1S)
Four-layer (2s2p)
RθJA
Thermal resistance, junction
to ambient (natural
convection)
47
50
41
°C/W
°C/W
°C/W
1, 3
1, 3
1, 3
RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal resistance, junction
to board
35
20
5
32
23
8
34
20
5
33
24
6
°C/W
°C/W
°C/W
4
5
6
Thermal resistance, junction
to case
Thermal characterization
parameter, junction to
package top outside center
(natural convection)
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization.
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
18
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
