Switching specifications
5.2 Switching specifications
5.2.1 Control timing
Table 6. Control timing
Num
C
P
P
D
Rating
Bus frequency (tcyc = 1/fBus
Symbol
fBus
Min
DC
Typical1
Max
20
Unit
MHz
KHz
ns
1
2
3
)
—
1.0
—
Internal low power oscillator frequency
External reset pulse width
fLPO
0.67
1.25
—
textrst
1.5 ×
tcyc
4
5
D
D
Reset low drive
trstdrv
tILIH
34 × tcyc
100
—
—
—
—
ns
ns
IRQ pulse width
Asynchronous
path2
D
D
Synchronous path
tIHIL
tILIH
1.5 × tcyc
100
—
—
—
—
ns
ns
6
7
Keyboard interrupt pulse
width
Asynchronous
path2
D
C
C
Synchronous path
—
tIHIL
tRise
tFall
1.5 × tcyc
—
10.2
9.5
—
—
—
ns
ns
ns
Port rise and fall time -
Normal drive strength
(load = 50 pF)
—
—
C
C
Port rise and fall time -
high drive strength (load =
50 pF)3
—
tRise
tFall
—
—
5.4
4.6
—
—
ns
ns
1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a RESET pin request.
3. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 105 °C.
textrst
RESET_b pin
Figure 9. Reset timing
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 10. KBIPx timing
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
16
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
