Peripheral operating requirements and behaviors
TCLK
J9
J10
Input data valid
TDI/TMS
TDO
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 8. Test Access Port timing
TCLK
TRST
J14
J13
Figure 9. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
K51 Sub-Family Data Sheet, Rev. 2, 4/2012.
26
Freescale Semiconductor, Inc.