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MK51DX256CLK7 参数 Datasheet PDF下载

MK51DX256CLK7图片预览
型号: MK51DX256CLK7
PDF下载: 下载PDF文件 查看货源
内容描述: K51次家庭 [K51 Sub-Family]
分类和应用:
文件页数/大小: 77 页 / 1911 K
品牌: FREESCALE [ Freescale ]
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Peripheral operating requirements and behaviors  
6.3.1 MCG specifications  
Table 13. MCG specifications  
Symbol Description  
Min.  
Typ.  
Max.  
Unit  
Notes  
fints_ft Internal reference frequency (slow clock) —  
32.768  
kHz  
factory trimmed at nominal VDD and 25 °C  
fints_t  
Internal reference frequency (slow clock) — user  
trimmed  
31.25  
39.0625  
0.6  
kHz  
Δfdco_res_t Resolution of trimmed average DCO output  
frequency at fixed voltage and temperature —  
using SCTRIM and SCFTRIM  
0.3  
%fdco  
1
1
Δfdco_res_t Resolution of trimmed average DCO output  
frequency at fixed voltage and temperature —  
using SCTRIM only  
0.2  
0.5  
%fdco  
Δfdco_t  
Total deviation of trimmed average DCO output  
frequency over voltage and temperature  
+0.5/-0.7  
%fdco  
%fdco  
1
1
Δfdco_t  
Total deviation of trimmed average DCO output  
frequency over fixed voltage and temperature  
range of 0–70°C  
fintf_ft  
Internal reference frequency (fast clock) —  
factory trimmed at nominal VDD and 25°C  
3
4
5
MHz  
MHz  
kHz  
kHz  
fintf_t  
Internal reference frequency (fast clock) — user  
trimmed at nominal VDD and 25 °C  
floc_low  
Loss of external clock minimum frequency —  
RANGE = 00  
(3/5) x  
fints_t  
floc_high  
Loss of external clock minimum frequency —  
RANGE = 01, 10, or 11  
(16/5) x  
fints_t  
FLL  
ffll_ref  
fdco  
FLL reference frequency range  
31.25  
20  
39.0625  
25  
kHz  
DCO output  
Low range (DRS=00)  
640 × ffll_ref  
20.97  
MHz  
2, 3  
frequency range  
Mid range (DRS=01)  
1280 × ffll_ref  
40  
60  
80  
41.94  
62.91  
83.89  
50  
75  
MHz  
MHz  
MHz  
Mid-high range (DRS=10)  
1920 × ffll_ref  
High range (DRS=11)  
2560 × ffll_ref  
100  
Table continues on the next page...  
K51 Sub-Family Data Sheet, Rev. 2, 4/2012.  
Freescale Semiconductor, Inc.  
27