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MK51DX256CLK7 参数 Datasheet PDF下载

MK51DX256CLK7图片预览
型号: MK51DX256CLK7
PDF下载: 下载PDF文件 查看货源
内容描述: K51次家庭 [K51 Sub-Family]
分类和应用:
文件页数/大小: 77 页 / 1911 K
品牌: FREESCALE [ Freescale ]
 浏览型号MK51DX256CLK7的Datasheet PDF文件第24页浏览型号MK51DX256CLK7的Datasheet PDF文件第25页浏览型号MK51DX256CLK7的Datasheet PDF文件第26页浏览型号MK51DX256CLK7的Datasheet PDF文件第27页浏览型号MK51DX256CLK7的Datasheet PDF文件第29页浏览型号MK51DX256CLK7的Datasheet PDF文件第30页浏览型号MK51DX256CLK7的Datasheet PDF文件第31页浏览型号MK51DX256CLK7的Datasheet PDF文件第32页  
Peripheral operating requirements and behaviors  
Table 13. MCG specifications (continued)  
Symbol Description  
Min.  
Typ.  
Max.  
Unit  
Notes  
fdco_t_DMX3 DCO output  
Low range (DRS=00)  
732 × ffll_ref  
23.99  
MHz  
4, 5  
frequency  
2
Mid range (DRS=01)  
1464 × ffll_ref  
47.97  
71.99  
95.98  
MHz  
MHz  
MHz  
ps  
Mid-high range (DRS=10)  
2197 × ffll_ref  
High range (DRS=11)  
2929 × ffll_ref  
Jcyc_fll  
FLL period jitter  
180  
150  
• fVCO = 48 MHz  
• fVCO = 98 MHz  
tfll_acquire FLL target frequency acquisition time  
1
ms  
6
PLL  
fvco  
Ipll  
VCO operating frequency  
48.0  
100  
MHz  
µA  
PLL operating current  
7
7
1060  
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref  
2 MHz, VDIV multiplier = 48)  
=
=
Ipll  
PLL operating current  
600  
µA  
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref  
2 MHz, VDIV multiplier = 24)  
fpll_ref  
PLL reference frequency range  
2.0  
4.0  
MHz  
Jcyc_pll  
PLL period jitter (RMS)  
• fvco = 48 MHz  
8
8
120  
50  
ps  
ps  
• fvco = 100 MHz  
Jacc_pll  
PLL accumulated jitter over 1µs (RMS)  
• fvco = 48 MHz  
1350  
600  
ps  
ps  
• fvco = 100 MHz  
Dlock  
Dunl  
Lock entry frequency tolerance  
Lock exit frequency tolerance  
Lock detector detection time  
1.49  
4.47  
2.98  
5.97  
%
%
s
150 × 10-6  
+ 1075(1/  
tpll_lock  
9
fpll_ref  
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock  
mode).  
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.  
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation  
(Δfdco_t) over voltage and temperature should be considered.  
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.  
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.  
K51 Sub-Family Data Sheet, Rev. 2, 4/2012.  
28  
Freescale Semiconductor, Inc.