Peripheral operating requirements and behaviors
Table 35. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Operating voltage
Frequency of operation
—
6.25
—
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
ns
ns
ns
ns
ns
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
24
—
—
—
19
19
3.2
7
—
—
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 18. DSPI classic SPI timing — slave mode
I2C switching specifications
6.8.6
See General switching specifications.
6.8.7 UART switching specifications
See General switching specifications.
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
49
FREESCALE [ Freescale ]
