Peripheral operating requirements and behaviors
6.8.5 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 34. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
12.5
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
(tSCK/2) - 4 (tSCK/2) + 4
ns
ns
(tBUS x 2) −
4
—
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-1.2
19.1
0
8.5
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 17. DSPI classic SPI timing — master mode
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
48
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
