Freescale Semiconductor, Inc.
RECEIVER
BAUD RATE
CLOCK
DDD0
÷16
10 (11) - BIT
Rx SHIFT REGISTER
S
S
PIN BUFFER
AND CONTROL
DATA
RECOVERY
PD0/
RxD
(8)
7
6
5
4
3
2
1
0
MSB
ALL ONES
DISABLE
DRIVER
RE
M
WAKE-UP
LOGIC
RWU
8
SCCR1 SCI CONTROL 1
SCSR1 SCI STATUS 1
SCDR Rx BUFFER
(READ-ONLY)
8
RDRF
RIE
IDLE
ILIE
8
OR
RIE
SCCR2 SCI CONTROL 2
SCI Tx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 7-2 SCI Receiver Block Diagram
SERIAL COMMUNICATIONS INTERFACE
TECHNICAL DATA
7-3
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