Freescale Semiconductor, Inc.
HIGHEST
POWER-ON RESET
(POR)
PRIORITY
EXTERNAL RESET
DELAY 4064 E CYCLES
CLOCK MONITOR FAIL
(WITH CME = 1)
LOWEST
COP WATCHDOG TIMEOUT
(WITH NOCOP = 0)
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFE, FFFF (VECTOR FETCH)
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFC, FFFD (VECTOR FETCH)
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFA, FFFB (VECTOR FETCH)
SET S, X, AND I BITS
IN CCR
RESET MCU
HARDWARE
1A
BEGIN AN INSTRUCTION
SEQUENCE
X BIT IN
CCR SET
?
YES
NO
XIRQ
PIN LOW
?
YES
NO
STACK CPU
REGISTERS
SET X AND I BITS
FETCH VECTOR
$FFE4, FFE5
1B
Figure 5-1 Processing Flow Out of Reset (1 of 2)
RESETS AND INTERRUPTS
MC68HC11F1
5-12
TECHNICAL DATA
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