Freescale Semiconductor, Inc.
1B
I BIT IN
CCR SET
?
YES
NO
ANY I BIT
INTERRUPT
PENDING
?
YES
NO
FETCH OPCODE
STACK CPU
REGISTERS
ILLEGAL
OPCODE
?
YES
STACK CPU
REGISTERS
SET X AND I BITS
NO
FETCH VECTOR
$FFE8, FFE9
YES
STACK CPU
REGISTERS
WAI
?
NO
NO
INTERRUPT
YES
YES
STACK CPU
REGISTERS
SWI
?
YET
?
SET X AND I BITS
YES
NO
FETCH VECTOR
$FFE6, FFE7
SET I BIT
RTI
?
RESTORE CPU
REGISTERS
FROM STACK
NO
RESOLVE INTERRUPT
PRIORITY AND FETCH
VECTOR FOR HIGHEST
PENDING SOURCE
EXECUTE THIS
INSTRUCTION
(REFER TO FIGURE 5-2)
START NEXT
INSTRUCTION
SEQUENCE
1A
Figure 5-2 Processing Flow Out of Reset (2 of 2)
RESETS AND INTERRUPTS
TECHNICAL DATA
5-13
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