Freescale Semiconductor, Inc.
BEGIN
YES
RDRF = 1
?
NO
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
OR = 1
?
RIE = 1
?
RE = 1
?
NO
NO
NO
TDRE = 1
?
TIE = 1
?
TE = 1
?
NO
NO
NO
TC = 1
?
TCIE = 1
?
NO
NO
YES
IDLE = 1
?
ILIE = 1
?
RE = 1
?
NO
NO
NO
NO – VALID SCI
REQUEST
YES – VALID SCI
REQUEST
Figure 5-5 Interrupt Source Resolution Within SCI
5.5 Low Power Operation
Both STOP and WAIT suspend CPU operation until a reset or interrupt occurs. The
WAIT condition suspends processing and reduces power consumption to an interme-
diate level. The STOP condition turns off all on-chip clocks and reduces power con-
sumption to an absolute minimum while retaining the contents of all 1024 bytes of
RAM.
RESETS AND INTERRUPTS
MC68HC11F1
5-16
TECHNICAL DATA
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