Electrical Characteristics
Table 24. I C Input Timing Specifications between I2C_SCL and I2C_SDA
2
Num
Characteristic
Start condition hold time
Min
Max
Units
11
I2
I3
I4
I5
I6
I7
I8
I9
2 × tCYC
8 × tCYC
—
—
—
1
ns
ns
ms
ns
ms
ns
ns
ns
ns
Clock low period
SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
Data hold time
0
—
1
SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
Clock high time
—
4 × tCYC
0
—
—
—
—
Data setup time
Start condition setup time (for repeated start condition only)
Stop condition setup time
2 × tCYC
2 × tCYC
2
Table 25 lists specifications for the I C output timing parameters shown in Figure 13.
2
Table 25. I C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
111 Start condition hold time
6 × tCYC
10 × tCYC
—
—
—
—
ns
ns
μs
I21
I32
Clock low period
I2C_SCL/I2C_SDA rise time
(VIL = 0.5 V to VIH = 2.4 V)
I41
I53
Data hold time
7 × tCYC
—
3
ns
ns
I2C_SCL/I2C_SDA fall time
(VIH = 2.4 V to VIL = 0.5 V)
—
I61
I71
I81
Clock high time
Data setup time
10 × tCYC
2 × tCYC
—
—
—
ns
ns
ns
Start condition setup time (for repeated start
condition only)
20 × tCYC
I91
Stop condition setup time
10 × tCYC
—
ns
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 25. The I2C
interface is designed to scale the actual data transition time to move it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed into the IFDR;
however, the numbers given in Table 25 are minimum values.
2
3
Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive
low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
Specified at a nominal 50-pF load.
MCF52259 ColdFire Microcontroller, Rev. 0
Freescale Semiconductor
41
FREESCALE [ Freescale ]
