Electrical Characteristics
1
Table 26. ADC Parameters (continued)
Name
Characteristic
Min
Typical
Max
Unit
SNR
THD
Signal-to-noise ratio
—
—
62 to 66
−75
—
—
—
—
—
dB
dB
Total harmonic distortion
Spurious free dynamic range
SFDR
—
67 to 70.3
61 to 63.9
10.6
dB
SINAD Signal-to-noise plus distortion
ENOB Effective number of bits
—
dB
9.1
Bits
1
2
3
4
5
6
7
All measurements are preliminary pending full characterization, and made at VDD = 3.3V, VREFH = 3.3V, and VREFL = ground
INL measured from VIN = VREFL to VIN = VREFH
LSB = Least Significant Bit
INL measured from VIN = 0.1VREFH to VIN = 0.9VREFH
Includes power-up of ADC and VREF
ADC clock cycles
Current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC
2.15 Equivalent Circuit for ADC Inputs
Figure 10-17 shows the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3
is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and hold circuit moves to (VREFH-VREFL)/2, while
the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with
the result that a single-ended analog input is switched to a differential voltage centered about (VREFH-VREFL)/2. The switches
switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). There are additional
capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides
isolation during the charge-sharing phase. One aspect of this circuit is that there is an on-going input current, which is a function
of the analog input voltage, VREF and the ADC clock frequency.
125W ESD Resistor
8pF noise damping capacitor
3
4
Analog Input
S1
C1
C2
S/H
S3
(VREFH- VREFL)/ 2
S2
2
1
C1 = C2 = 1pF
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF
3. Equivalent resistance for the channel select mux; 100 Ωs
4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1.4pF
1
5. Equivalent input impedance, when the input is selected =
(ADC Clock Rate) × (1.4×10-12
)
Figure 14. Equivalent Circuit for A/D Loading
MCF52259 ColdFire Microcontroller, Rev. 0
Freescale Semiconductor
43
FREESCALE [ Freescale ]
