Electrical Characteristics
Table 29. JTAG and Boundary Scan Timing
Num
Characteristics1
TCLK frequency of operation
Symbol
Min
Max
Unit
J1
fJCYC
tJCYC
DC
1/4
—
—
3
fsys/2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
J2
TCLK cycle period
4 × tCYC
J3
TCLK clock pulse width
tJCW
26
0
J4
TCLK rise and fall times
tJCRF
J5
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI Input data hold time after TCLK rise
TCLK low to TDO data valid
tBSDST
tBSDHT
tBSDV
4
—
—
33
33
—
—
26
8
J6
26
0
J7
J8
tBSDZ
0
J9
tTAPBST
tTAPBHT
tTDODV
tTDODZ
tTRSTAT
tTRSTST
4
J10
J11
J12
J13
J14
10
0
TCLK low to TDO high Z
0
TRST assert time
100
10
—
—
TRST setup time (negation) to TCLK high
1
JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.
J2
J3
J3
VIH
TCLK
(input)
VIL
J4
J4
Figure 16. Test Clock Input Timing
MCF52259 ColdFire Microcontroller, Rev. 0
Freescale Semiconductor
45
FREESCALE [ Freescale ]
