Electrical Characteristics
Table 15. Oscillator and PLL Specifications (continued)
(VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V)
Characteristic
Frequency un-LOCK range
Symbol
Min
Max
Unit
fUL
–1.5
1.5
% fref
% fref
Frequency LOCK range
fLCK
Cjitter
–0.75
0.75
CLKOUT period jitter 4, 5, 9 ,10, measured at fSYS Max
• Peak-to-peak (clock edge to clock edge)
• Long term (averaged over 2 ms interval)
—
—
10
.01
% fsys
MHz
On-chip oscillator frequency
foco
7.84
8.16
1
2
3
4
5
In external clock mode, it is possible to run the chip directly from an external clock source without enabling the PLL.
All internal registers retain data at 0 Hz.
Depending on packaging; see Table 12.
Loss of Reference Frequency is the reference frequency detected internally, which transitions the PLL into self clocked mode.
Self clocked mode frequency is the frequency at which the PLL operates when the reference frequency falls below fLOR with
default MFD/RFD settings.
6
7
8
This parameter is characterized before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
9
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the Cjitter percentage
for a given interval.
10 Based on slow system clock of 40 MHz measured at fsys max.
2.8
USB Operation
Table 16. USB Operation Specifications
Characteristic
Symbol
Value
Unit
Minimum core speed for USB operation
fsys_USB_min
16
MHz
2.9
Mini-FlexBus External Interface Specifications
A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to interface to slave-only
devices up to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such
as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional
circuitry. For asynchronous devices a simple chip-select based interface can be used.
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of
a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus frequency.
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Mini-FlexBus output
clock (MB_CLK). All other timing relationships can be derived from these values.
MCF52259 ColdFire Microcontroller, Rev. 0
Freescale Semiconductor
35
FREESCALE [ Freescale ]
