Memories and memory interfaces
Table 20. EzPort switching specifications (continued)
Num
EP3
EP4
EP5
EP6
EP7
EP8
EP9
Description
Min.
15
Max.
—
Unit
ns
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
0.0
15
—
ns
—
ns
0.0
—
—
ns
25
—
ns
0.0
—
ns
12
ns
EZP_CK
EP3
EP4
EP2
EZP_CS
EP9
EP8
EP7
EP6
EZP_Q (output)
EZP_D (input)
EP5
Figure 6. EzPort Timing Diagram
6.4.3 Mini-Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
MCF51JU128 Data Sheet, Rev. 4, 01/2012.
32
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
