Memories and memory interfaces
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Mini-Flexbus output clock (FB_CLK). All other timing relationships
can be derived from these values.
Table 21. Flexbus switching specifications
Num
Description
Min.
1.71
—
Max.
3.6
25
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
MHz
ns
FB1
FB2
FB3
FB4
FB5
40
—
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
—
20
ns
1
1
2
2
1
—
ns
20
—
ns
10
—
ns
1. Specification is valid for all FB_AD[31:0], FB_CSn, FB_OE, FB_R/W, and FB_TS.
2. Specification is valid for all FB_AD[31:0].
Note
The following diagrams refer to signal names that may not be
included on your particular device. Ignore these extraneous
signals.
Also, ignore the AA=0 portions of the diagrams because this
setting is not supported in the Mini-FlexBus.
MCF51JU128 Data Sheet, Rev. 4, 01/2012.
Freescale Semiconductor, Inc.
33
FREESCALE [ Freescale ]
